Implementation of HEVC intra 4×4 prediction on FPGA

The last video coding standard HEVC (High Efficiency Video Coding) achieves 50% bit rate reduction relative to H.264 at the same visual quality. However, this new standard involves increased complexity compared to its predecessor. Intra prediction plays an important role in video encoders, especially in HEVC. The aim of this paper is to present hardware implementation of HEVC Intra 4×4 prediction algorithm on Xilinx Spartan-3E XC3S200 FPGA chip. The proposed architecture performed DC mode and angular modes for Intra 4×4 Prediction. Simulation results and synthesizing on Xilinx Spartan-3E FPGA of the HEVC intra 4×4 prediction algorithms demonstrate the accuracy and the efficiency of the proposed architecture.