• DocumentCode
    2034115
  • Title

    High-speed IDDQ measurement circuit

  • Author

    Isawa, K. ; Hashimoto, Yoshihiro

  • Author_Institution
    Advantest Corp., Saitama, Japan
  • fYear
    1996
  • fDate
    20-25 Oct 1996
  • Firstpage
    112
  • Lastpage
    117
  • Abstract
    The IDDQ test is an effective means of testing CMOS ICs that contain a high level of integration. However, the test presents a practical disadvantage due to the low test rate of less than 50 kHz. A new circuit was designed in an attempt to realize a higher test rate. When evaluated by simulation at a target current level of 1 μA, the new circuit demonstrated a potential test rate of 1 MHz in continuous testing
  • Keywords
    CMOS digital integrated circuits; electric current measurement; integrated circuit testing; 1 MHz; 1 muA; CMOS ICs; IDDQ test; IC testing; high-speed IDDQ measurement circuit; quiescent power supply current; Circuit simulation; Circuit testing; Current measurement; Current supplies; Integrated circuit testing; Load management; Power measurement; Power supplies; Velocity measurement; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1996. Proceedings., International
  • Conference_Location
    Washington, DC
  • ISSN
    1089-3539
  • Print_ISBN
    0-7803-3541-4
  • Type

    conf

  • DOI
    10.1109/TEST.1996.556952
  • Filename
    556952
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2034115