DocumentCode :
2034161
Title :
Packaging challenges for small die
Author :
Chin Hui Chong ; Yong Kian Tan
Author_Institution :
Micron Semicond. Asia, Singapore, Singapore
fYear :
2012
fDate :
5-7 Dec. 2012
Firstpage :
384
Lastpage :
388
Abstract :
During the last few years, wafer technology has been shrinking aggressively from the 50nm node down to a much smaller technology node. This creates a disparity between die and packaging in which the die is miniaturizing, yet the packaging´s physical footprint remains unchanged. Among the various packaging types, the one that is most impacted is board-on-chip (BOC) packaging, which is the current mainstream packaging for DDR2/DDR3 devices. The construction of the BOC package is a one-layer interposer with a window cut-out along the center; the die´s active circuit faces down with respect to the package footprint. The interconnect between the die and package is wire, via the window cut-out. As the die shrinks, and the package footprint remains unchanged, one of the design bottlenecks is the trace fan-out issue from the bond finger to the innermost column of the ball, as well as the tighter bond finger pitch due to the die-pad pitch reduction. This paper will describe the design features that need be addressed for small-die packages - for example, the drive toward fine line trace, wire bond top pad width, and narrower bond slots. A test vehicle is tooled up as a simulation of possible manufacturing/process issues for the small-die package solution. The design and analysis of the experiment are described in full in this paper.
Keywords :
integrated circuit bonding; integrated circuit packaging; microassembling; active circuit; board-on-chip packaging; bond finger; design bottleneck; die-pad pitch reduction; one-layer interposer; package footprint; packaging challenges; small die package; trace fan-out issue; wafer technology; Conductors; Copper; Fingers; Packaging; Routing; Substrates; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Packaging Technology Conference (EPTC), 2012 IEEE 14th
Conference_Location :
Singapore
Print_ISBN :
978-1-4673-4553-8
Electronic_ISBN :
978-1-4673-4551-4
Type :
conf
DOI :
10.1109/EPTC.2012.6507112
Filename :
6507112
Link To Document :
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