A novel low power and high speed Wallace tree multiplier for RISC processor

Power dissipation of integrated circuits is a major concern for VLSI circuit designers. A Wallace tree multiplier is an improved version of tree based multiplier architecture. It uses carry save addition algorithm to reduce the latency. This paper aims at additional reduction of latency and power consumption of the Wallace tree multiplier. This is accomplished by the use of 4:2, 5:2 compressors and by the use of Sklansky adder. The result shows that the proposed architecture is 44.4% faster than the conventional CMOS architecture, along with 11% of reduced power consumption realization at 200MHz. The simulations have been carried out using the TANNER EDA tool employing the 350nm CMOS technology library file from Austria Micro System.