The Effect of Wafer Substrate Resistance on Inter Poly Oxide Thickness Variation

Author

Towner, Janet M. ; Naughton, John J.

Author_Institution

AMI Semicond., Inc., Pocatello, ID

fYear

2006

fDate

22-24 May 2006

Firstpage

395

Lastpage

399

Abstract

In our mixed signal devices, deposited oxides are used in structures such as poly-poly capacitors. Wafers using highly doped substrates showed good thickness uniformity but uniformity deteriorated as the resistance of the substrate increased. Other factors that increased substrate resistance also increased nonuniformity. Thickness variation was correlated to electrostatic charge imparted to the wafer from poorly grounded wafer handling robotics. This charging likely caused plasma instabilities that promoted the absorption and reaction of the TEOS intermediates

Keywords

integrated circuit manufacture; integrated circuit technology; mixed analogue-digital integrated circuits; plasma CVD; PECVD TEOS deposition; capacitor oxide; doped substrates; electrostatic charging; grounded wafer handling robotics; inter poly oxide thickness; mixed signal devices; plasma instabilities; poly-poly capacitors; thickness variation; wafer substrate resistance; Ambient intelligence; Application specific integrated circuits; Capacitors; Electrostatics; Manufacturing processes; Plasma applications; Plasma chemistry; Plasma immersion ion implantation; Plasma materials processing; Substrates;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Manufacturing Conference, 2006. ASMC 2006. The 17th Annual SEMI/IEEE

Conference_Location

Boston, MA

ISSN

1078-8743

Print_ISBN

1-4244-0254-9

Type

conf

DOI

10.1109/ASMC.2006.1638790

Filename

1638790