DocumentCode :
2034294
Title :
Efficient linear feedback shift register design for pseudo exhaustive test generation in BIST
Author :
Haridas, Nisha ; Devi, M. Nirmala
Author_Institution :
II MTech, Amrita Vishwa Vidyapeetham, Coimbatore, India
Volume :
1
fYear :
2011
fDate :
8-10 April 2011
Firstpage :
350
Lastpage :
354
Abstract :
Pattern generation is the most important module in a BIST. Out of many test pattern generators (TPG) explored for BIST, linear feedback shift registers (LFSR) are widely used due to their ability to produce highly random patterns. Various improvements over the basic forms of LFSR are available. In the current study, the selection of an appropriate LFSR for a given benchmark circuit is analyzed. It is done by considering various factors such as selection of characteristic polynomial and seed to obtain high fault coverage, minimize invalid patterns, area overhead and time taken to generate the patterns.
Keywords :
automatic test pattern generation; built-in self test; circuit feedback; logic design; polynomials; shift registers; BIST; benchmark circuit; built-in self-test; characteristic polynomial; fault coverage; linear feedback shift register design; pattern generation; pseudo exhaustive test generation; test pattern generator; Built-in self-test; Circuit faults; Computers; Polynomials; Test pattern generators; Very large scale integration; BIST; Characteristic polynomial; LFSR; seed selection;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Computer Technology (ICECT), 2011 3rd International Conference on
Conference_Location :
Kanyakumari
Print_ISBN :
978-1-4244-8678-6
Electronic_ISBN :
978-1-4244-8679-3
Type :
conf
DOI :
10.1109/ICECTECH.2011.5941621
Filename :
5941621
Link To Document :
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