Title :
High Volume Manufacturing Ramp In 90nm Dual Stress Liner Technology
Author :
Gehres, R. ; Malik, R. ; Amos, R. ; Brown, J. ; Butt, S. ; Chan, A. ; Collins, C. ; Colwill, B. ; Davies, B. ; Gabor, A. ; Le, N. ; Lindo, P. ; Mello, K. ; Meyette, E. ; Nastasi, V. ; Patrick, J. ; Piper, A. ; Prakash, D.P. ; Rust, T. ; Santiago, A. ; Su,
Author_Institution :
IBM Syst. & Technol. Group, Hopewell Junction, NY
Abstract :
The ability to meet the demand for improved microprocessor performance is made difficult due to the simultaneous need not to increase power consumption. In order to meet these conflicting demands, IBM introduced a 90 nm dual stress liner CMOS technology to improve performance without increasing power consumption (Santiago et al., 2006). In IBM´s 300 mm fab, this technology was introduced on multiple microprocessors, designed by different design groups with different architectures. These microprocessors, which were originally designed for a single liner technology, were optimized for systematic yield, power/performance; circuit limited yield (CLY), and random defect limited yield. The benefit of the dual stress liner technology is demonstrated in the power/performance characteristic of a dual core microprocessor and the successful technology ramp is demonstrated by yields of two microprocessors
Keywords :
CMOS integrated circuits; integrated circuit yield; microprocessor chips; 300 mm; 90 nm; CMOS technology; IBM; circuit limited yield; dual core microprocessor; dual stress liner technology; high volume manufacturing ramp; multiple microprocessors; nanofabrication; power consumption; random defect limited yield; systematic yield; CMOS technology; Circuits; Compressive stress; Design optimization; Hardware; Manufacturing; Microprocessors; Process design; Production; Tensile stress;
Conference_Titel :
Advanced Semiconductor Manufacturing Conference, 2006. ASMC 2006. The 17th Annual SEMI/IEEE
Conference_Location :
Boston, MA
Print_ISBN :
1-4244-0254-9
DOI :
10.1109/ASMC.2006.1638793
