Title :
Stacking of known good rebuilt wafers with Through Polymer Via based 3D interconnect application to high speed DDR3
Author :
Noiray, B.J. ; Val, Celina ; Couderc, Paul
Author_Institution :
3D PLUS, Buc, France
Abstract :
Based on Wire free Die on Die disruptive technology (WDoDTM), high density memories have been manufactured in a small form factor package size [1]. 3D-Plus process flow is very much focused on niche markets such as defense, industrial and medical applications. However a new integration scheme based on Through Polymer Via enables a turnkey solution for high volume manufacturing of 3D packages.
Keywords :
DRAM chips; integrated circuit interconnections; polymers; three-dimensional integrated circuits; wafer level packaging; 3D interconnect application; 3D package high volume manufacturing; 3D-plus process flow; WDoD; factor package size; high density memories; high speed DDR3; niche markets; rebuilt wafers; through polymer via; wire free die on die disruptive technology; Metallization; Polymers; Resins; Silicon compounds; Stacking; 3D packaging; TPV; WDoD; polymer bonding; reconstructed wafer; system in package;
Conference_Titel :
Electronics Packaging Technology Conference (EPTC), 2012 IEEE 14th
Conference_Location :
Singapore
Print_ISBN :
978-1-4673-4553-8
Electronic_ISBN :
978-1-4673-4551-4
DOI :
10.1109/EPTC.2012.6507121
