Reduced comparator low power flash ADC using 35nm CMOS

Author

Varma, Dharmendra Mani

Author_Institution

Dept. of Microelectron., Indian Inst. of Inf. Technol., Allahabad, India

Volume

1

fYear

2011

fDate

8-10 April 2011

Firstpage

385

Lastpage

388

Abstract

ADC is one of the basic elements in digital system, as we need to interconnect the digital system to real world that is analog, so these are a primary and important block of any digital system. In this paper, a new design for a low power CMOS flash ADC is proposed. A 4 bit flash ADC with maximum acquisition speed of 2Gs/s, is implemented with 1.2V supply voltage. Hspice simulation result for proposed architecture verifying the analytical result is given. It shows that the proposed ADC consumes about 24mW. The INL/DNL is 0.34/0.4. This is due to reduction in number of comparators as compared to normal flash ADC. By reduced no of comparator.

Keywords

CMOS digital integrated circuits; SPICE; analogue-digital conversion; low-power electronics; Hspice simulation; acquisition speed; low power CMOS flash ADC; reduced comparator low power flash ADC; size 35 nm; voltage 1.2 V; word length 4 bit; CMOS integrated circuits; Conferences; Digital systems; Multiplexing; Power demand; Simulation; Solid state circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics Computer Technology (ICECT), 2011 3rd International Conference on

Conference_Location

Kanyakumari

Print_ISBN

978-1-4244-8678-6

Electronic_ISBN

978-1-4244-8679-3

Type

conf

DOI

10.1109/ICECTECH.2011.5941628

Filename

5941628