A new bus coding technique to minimize crosstalk in VLSI bus

In DSM technology, minimizing the propagation delay and power consumption on buses is the most important design objective in system-on-chip design. In particular, the coupling effects between wires on the bus that can cause serious problems such as crosstalk delay, noise and power consumption. This paper proposes a technique which reduces power consumption data buses which are fed to a DSP/Communication device. The proposed coding technique reduces the transition activity in the input signals and will consequently result in the reduction of power consumption. A new bus coding technique has been proposed to achieve less power reduction in transmission. SPICE simulations are carried out for interconnect lines of different dimensions at various technology nodes (180, 130, 90 and 65 nm). The proposed model reduces the power consumption by upto 35%.