Design and implementation of low power digital FIR filter based on low power multipliers and adders on xilinx FPGA

This paper presents the methods to reduce dynamic power consumption of a digital Finite Imppulse Respanse (FIR) filter these mrthods include low power serial multiplier and serial adder, combinational booth multiplier, shift/add multipliers, folding transformation in linear phase architecture and applied to fir filters to power consumption reduced thus reduce power consumption due to glitching is also reduced. The minimum power achieved is 110mw in fir filter based on shift/add multiplier in 100MHZ to 8taps and 8bits inputs and 8bits coefficions. The proposed FIR filters were synthesized implemented using Xilinx ISE Virtex IV FPGA and power is analized using Xilinx XPower analyzer.