Design and test of memory management unit and cache controller chip

Author

Hsieh, D. ; Feipei Lai

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

1

fYear

1993

fDate

19-21 Oct. 1993

Firstpage

10

Abstract

A design and test of memory management unit and cache controller (MMU/CC) chip for the Multiprocessor Architecture Reconciling Symbolic with numerical processing (MARS) are presented in this paper. MMU/CC can provide the memory access requirement of the MARS system for one load per cycle in the absence of cache miss, TLB miss, exception or interrupt. Not only the cache and memory operations are supported, but also an invalidation cache coherence protocol is embedded. The MMU/CC chip has 66290 transistors and 144 pins. The die size is 8653 /spl mu/m * 7114 /spl mu/m. We take a detailed look at critical issues of the design trade-offs, floor-planning, and testing.<>

Keywords

buffer storage; storage management; 144 pins; 66290 transistors; 7114 micron; 8653 micron; MARS; MMU/CC; Multiprocessor Architecture Reconciling Symbolic; cache coherence protocol; cache controller; design trade-offs; die size; floor-planning; memory access requirement; memory management unit; memory management unit and cache controller chip; testing; Access protocols; Central Processing Unit; Hardware; Mars; Memory management; Multiprocessing systems; Multiprocessor interconnection networks; Pins; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON '93. Proceedings. Computer, Communication, Control and Power Engineering.1993 IEEE Region 10 Conference on

Conference_Location

Beijing, China

Print_ISBN

0-7803-1233-3

Type

conf

DOI

10.1109/TENCON.1993.319916

Filename

319916