Title :
A machine-description table based instruction scheduler for improving pipeline execution parallelism on QHRC RISC system
Author :
Li Sanli ; Fu Xinggang
Author_Institution :
Dept. of Comput., Tsinghua Univ., Beijing, China
Abstract :
This paper presents a parameterized instruction scheduling algorithm based on machine description table for QHRC RISC system, having a 3-5 stage pipeline structure. It would provide considerable flexibility for instruction scheduling, improving execution efficiency for rapidly upgrading RISC machines. And, using this instruction scheduler as a tool, the effect of several methods for solving instruction interlock problem has been analysed. Finally, a high performance approach combining the hardware feasibility and software effectiveness for solving instruction interlock problem and enhancing pipeline execution parallelism is given.<>
Keywords :
computational complexity; parallel architectures; scheduling; QHRC RISC; execution efficiency; instruction interlock; instruction scheduler; machine-description table; parameterized instruction scheduling; pipeline execution; pipeline execution parallelism; Circuits; Computer architecture; Job shop scheduling; Mesons; Parallel processing; Pipeline processing; Processor scheduling; Reduced instruction set computing; Registers; Scheduling algorithm;
Conference_Titel :
TENCON '93. Proceedings. Computer, Communication, Control and Power Engineering.1993 IEEE Region 10 Conference on
Conference_Location :
Beijing, China
Print_ISBN :
0-7803-1233-3
DOI :
10.1109/TENCON.1993.319917
