Title :
An efficient division algorithm and its architecture
Author :
Sau-Gee Chen ; Chieh-Chih Li
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
In this work, a fast division algorithm and its time/area efficient architecture is proposed. It achieves the best performance in both area and speed aspects over the existing algorithms and implementations. The proposed architecture basically consists of N simple carry-save adders (CSAs) for bit-serial/serial implementation, and N/sup 2/ CSAs for bit parallel implementation. It finishes an N-bit division in 4N carry-save addition time and the result quotient is in binary representation. In addition, there is no complicated quotient decision circuit. Also a fast algorithm is developed to convert the signed-binary number representation to binary representation.<>
Keywords :
carry logic; computational complexity; digital arithmetic; binary representation; bit parallel implementation; carry-save adders; division algorithm; fast division algorithm; performance; time/area efficient architecture; Adders; Circuits; Convergence; Councils; Delay; Hardware;
Conference_Titel :
TENCON '93. Proceedings. Computer, Communication, Control and Power Engineering.1993 IEEE Region 10 Conference on
Conference_Location :
Beijing, China
Print_ISBN :
0-7803-1233-3
DOI :
10.1109/TENCON.1993.319919
