DocumentCode
2035053
Title
Exhaustive testing of Fused Multiply-Add RTL
Author
Burgess, Neil ; Lutz, David R.
Author_Institution
ARM, Austin, TX, USA
fYear
2013
fDate
3-6 Nov. 2013
Firstpage
405
Lastpage
406
Abstract
This paper describes the development and use of a short-wordlength (11-bit) Fused Multiply-Add (“FMA”) design. This “cut-down” design replicates the logic of our IEEE 754-2008 compliant FMA RTL, but the smaller size permits exhaustive testing. We present details of the complete test results and discuss the utility of the truncated FMA.
Keywords
floating point arithmetic; logic design; logic testing; IEEE 754-2008 compliant FMA RTL; cut-down design; fused multiply-add RTL exhaustive testing; short-wordlength FMA design; word length 11 bit; Computer bugs; Floating-point arithmetic; IEEE standards; Multiplexing; Process control; Testing; Vectors;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems and Computers, 2013 Asilomar Conference on
Conference_Location
Pacific Grove, CA
Print_ISBN
978-1-4799-2388-5
Type
conf
DOI
10.1109/ACSSC.2013.6810306
Filename
6810306
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