Design, simulation and realization of a parametrizable, configurable and modular asynchronous FIFO

Asynchronous FIFOs had become an important block in the new system designs. High speed IOs elasticity buffers, interfacing with system components like processor and memory and in general data transfers between two un-correlated clock domains are example of applications that needs asynchronous FIFOs. This paper presents the design and simulation of an asynchronous FIFO that is paramterizable in data interface width and memory depth. The FIFO flag thresholds are re-configurable at run time and are using a modular design approach in its implementation and in interfacing with other system components.