Fault tolerance and pipelining of VLSI combinational logic networks

On the basis of alternating logic and complementary logic, a new fault-tolerant design method named as alternate complementary logic is proposed. Some properties of this logic are analyzed and a scheme of the combinational network realizing an arbitrary alternate complementary logic function is proposed. Under the assumption of the stuck-fault model, the network has the capabilities of on-line self-testing and fault-masking, and its time-delay can be reduced by pipelining.<>