Title :
Distributing computational processes to an attached RISC processor by code translation
Author :
Chang, M.F. ; Chan, Y.K.
Author_Institution :
Dept. of Comput. Sci., City Polytech. of Hong Kong, Kowloon, Hong Kong
Abstract :
With the RISC architecture, it is now possible to attain supercomputing power on a single microprocessor chip. However, developing a stand-alone system harnessing their power could be slow and difficult. In this paper, we describe attaching RISC to a host computer which acts as a front-end platform. Instead of writing new compilers, library routines, and applications for the RISC, we translate existing application programs on the host computer for it. It means that ordinary software development tools of the host computer can be used for program development and debugging without the presence of the RISC. Once the program is ready, it can be automatically translated into RISC codes for execution on a host computer with the attached RISC microprocessor. Since all the I/O functions are now done by the host computer, all the user interfaces remain the same thus the distribution of the task to the attached RISC microprocessor is transparent to the user except for much higher performance.<>
Keywords :
microprocessor chips; parallel processing; program debugging; reduced instruction set computing; software engineering; attached RISC processor; code translation; computational processes; debugging; program development; single microprocessor chip; software development tools; supercomputing power; user interfaces; Application software; Computer architecture; Distributed computing; Joining processes; Microprocessor chips; Program processors; Programming; Reduced instruction set computing; Software libraries; Writing;
Conference_Titel :
TENCON '93. Proceedings. Computer, Communication, Control and Power Engineering.1993 IEEE Region 10 Conference on
Conference_Location :
Beijing, China
Print_ISBN :
0-7803-1233-3
DOI :
10.1109/TENCON.1993.319925