Improving gate level fault coverage by RTL fault grading

A practical RTL level testability analysis methodology is presented in the paper. Both RTL models and functional verification patterns are used in the RTL testability analysis. An RTL fault simulator which is the core of the methodology, is developed to support RTL testability analysis. It is able to generate quantitative RTL fault coverage and provide information for test pattern improvement to improve fault coverage and design modifications to improve testability at the RTL level. Experimental results show that RTL fault coverage is quite close to fault coverage achieved at the gate level when designs are completed and mapped to a technology library. The results also show that effort to improve fault coverage at the RTL level very likely results in corresponding improvement of fault coverage at the gate level. An investigation of some of the causes of difference between RTL fault coverage and actual gate level fault coverage is also reported in the paper