Title :
Asynchronous network node design for network-on-chip
Author :
Wang, Xin ; Siguenza-Tortosa, David ; Ahonen, Tapani ; Nurmi, Jari
Author_Institution :
Inst. of Digital & Comput. Syst., Tampere Univ. of Technol., Finland
Abstract :
A network node for Proteo network-on-chip (NoC) has been developed in order to support globally-asynchronous locally-synchronous (GALS) communication in an on-chip system. The network node presented in this paper was implemented as a synthesizable intellectual property (IP) block in register-transfer level (RTL) using VHDL. The proposed design applies both asynchronous and synchronous circuits to make the globally asynchronous data transfer rate between network nodes independent of local clocks.
Keywords :
asynchronous circuits; hardware description languages; industrial property; integrated circuit design; integrated circuit interconnections; network-on-chip; VHDL; asynchronous network node design; data transfer; globally-asynchronous locally-synchronous communication; intellectual property; network on chip; register transfer level; Asynchronous circuits; Circuit simulation; Circuit synthesis; Clocks; Computer networks; Integrated circuit interconnections; Network synthesis; Network-on-a-chip; Synchronization; System-on-a-chip;
Conference_Titel :
Signals, Circuits and Systems, 2005. ISSCS 2005. International Symposium on
Print_ISBN :
0-7803-9029-6
DOI :
10.1109/ISSCS.2005.1509849
