DSPTune: a performance evaluation toolset for the SHARC signal processor

Author

Sair, Suleyman ; Olivadoti, Guiseppe ; Kaeli, David ; Fridman, Jose

Author_Institution

Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA

fYear

2000

fDate

2000

Firstpage

51

Lastpage

57

Abstract

Performance tuning in the embedded systems domain poses a new set of challenges for software and hardware designers. Techniques proven to work for general purpose architectures cannot always be directly applied to the signal processor environment. Program analysis and simulation tools have been shown to be available in the analysis of general purpose microprocessors. We anticipate that similar tools will be needed to analyze the characteristics of signal processing architectures and applications as well. To meet this need, we have developed DSPTune, a program analysis toolset for the Analog Devices´ SHARC DSP. This paper describes our toolset, and provides examples of its use

Keywords

assembly language; digital signal processing chips; embedded systems; performance evaluation; software tools; virtual machines; Analog Devices; DSP; DSPTune; SHARC signal processor; embedded systems; general purpose microprocessors; performance evaluation toolset; performance tuning; simulation tools; Analytical models; Computer architecture; Embedded software; Embedded system; Hardware; Microprocessors; Signal analysis; Signal processing; Software design; Software performance;

fLanguage

English

Publisher

ieee

Conference_Titel

Simulation Symposium, 2000. (SS 2000) Proceedings. 33rd Annual

Conference_Location

Washington, DC

ISSN

1080-241X

Print_ISBN

0-7695-0598-8

Type

conf

DOI

10.1109/SIMSYM.2000.844900

Filename

844900