Processing of ultrathin wafers for power chip applications

Providing thinner and thinner Silicon is one of the key challenges in today´s semiconductor manufacturing. The thinner the wafer and thus the die, the thinner the package can be designed. Getting thinner devices is also a necessary precondition for Through Silicon Via (TSV) technology, in which a thin wafer is needed in order to create through-contacts in the die. While for standard wafer applications the driver for thinner Silicon wafers may be considered as “geometrical”, this is not the case for power chip application. Here, the main driver for using thinner Silicon in powerchip applications is directly linked to device performance. As the R_ds(on) is primarily a function of the device thickness and thus the wafer thickness, producing thinner Silicon provides not only geometrical advantages in the packaging process, but especially better performing devices. In order to fullill the demand for thinner and thus improved devices, International Rectifier (IR) has recently installed a 200 mm line for ultrathin wafers. In this paper, we will describe and discuss the thinning process that is implemented at IR.