DocumentCode :
2035576
Title :
A dynamic study of pad structure impact on bond pad/low-K layer stress in copper wire bond
Author :
Yang, Yubin B. ; Kumar, Narendra ; John, Deepak ; Hyman, R. ; Clive, F. ; Nathapong, S. ; Ramroth, W.
Author_Institution :
RnD, United Test & Assembly Center Ltd., Singapore, Singapore
fYear :
2012
fDate :
5-7 Dec. 2012
Firstpage :
654
Lastpage :
658
Abstract :
In recent years, many OSAT (Outsourced Semiconductor Assembly and Test) companies start to explore copper wire bond process, which is believed to be able to reduce the IC packaging cost. Copper wire also shows better electrical performance especially for fine wire. However, the reliability maintenance is not as easy as gold wire. Some companies encountered numerous problems in mass production although the copper wire is qualified in engineering stage. This paper is an attempt to understand the bond pad design impact on pad stress as well as the low K layer stress. In this paper, an axisymmetric transient nonlinear dynamic finite element analysis is developed to assist the understanding of copper wire bond process. In the modeling, only Aluminum pad and low-K layers of the bond pad structure are focused. 4 bond pad structures are selected for the stress comparison from Aluminum pad surface to chip low-K layer. Firstly, the stress on Al pad and low K layer is studied with our standard capillary design and bond pad at different stage. Then the capillary inner chamfer angle is varied from 50° to 120 ° to see the impact. Lastly, 4 bond pad structures are presented for comparison.
Keywords :
aluminium; copper; lead bonding; mass production; IC packaging cost reduction; OSAT company; aluminum pad; axisymmetric transient nonlinear dynamic finite element analysis; bond pad design impact; copper wire bond; electrical performance; low-K layer stress; mass production; outsourced semiconductor assembly company; outsourced semiconductor test company; pad structure impact; reliability maintenance; Bonding; Copper; Finite element analysis; Integrated circuits; Stress; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Packaging Technology Conference (EPTC), 2012 IEEE 14th
Conference_Location :
Singapore
Print_ISBN :
978-1-4673-4553-8
Electronic_ISBN :
978-1-4673-4551-4
Type :
conf
DOI :
10.1109/EPTC.2012.6507163
Filename :
6507163
Link To Document :
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