An FPGA-based hardware emulator for fast fault emulation

An FPGA-based hardware emulation system is shown to boost the speed of fault simulation for sequential circuits. The circuit is downloaded into the emulation system which emulates the faulty circuit´s behavior by synthesizing from the good circuit and the given fault list in a novel way. Fault injection is made easy by shifting the content of a fault injection chain, with which we get rid of the highly time-consuming bit-stream regeneration process. Experimental results for ISCAS-89 benchmark circuits show that the fault emulator is about twenty times faster than HOPE (parallel fault simulator). A parallel fault emulation approach is also proposed, in which faults that are not activated or with short propagation distance are screened off before fault emulation, and non-stem faults are collapsed into their equivalent stem faults, further reducing the number of faults actually emulated