Locally-connected Viterbi decoder architectures and their VLSI implementation for LDPC and convolutional codes

The applicability of the Viterbi add-compare-select (ACS) functional block to both convolutional and LDPC codes in various parallel implementations is investigated. To this end, a trellis representation for arbitrary LDPC codes must first be established. Then, a high-level architecture for a Viterbi-algorithm-based unified decoder is proposed. An in-depth exploration of the crucial path metrics (i.e ACS) functional block is then presented, where various locally-connected parallel structures at different speed-area points are explored. Some implementation results are provided, showing that the proposed structures offer high throughput, low latency, and a wide spectrum of speed-area trade-off point, depending on the specific topology that is chosen.