Title :
Performance of a Globally-Clocked Parallel Simulator
Author :
Peterson, Gregory D. ; Chamberlain, Roger D.
Author_Institution :
Washington University, USA
Abstract :
A performance model for a globally-clocked, discrete-event queueing network simulator is developed and validated against measured results. The use of architectural enhancements for improving the performance of the algorithm is investigated. Both scaled and fixed problem sizes are investigated, with a maximum measured scaled speedup of 47 and 64 processors. The model is very accurate, predicting runtime within 5% of measured results.
Keywords :
Clocks; Computational modeling; Computer simulation; Discrete event simulation; Hardware; Network servers; Parallel processing; Predictive models; Protocols; Synchronization;
Conference_Titel :
Parallel Processing, 1993. ICPP 1993. International Conference on
Conference_Location :
Syracuse, NY, USA
Print_ISBN :
0-8493-8983-6
DOI :
10.1109/ICPP.1993.144
