DocumentCode :
2035736
Title :
A formally verified deadlock-free routing function in a fault-tolerant NoC architecture
Author :
Alhussien, Abdulaziz ; Bagherzadeh, Nader ; Verbeek, Freek ; Van Gastel, Bernard ; Schmaltz, Julien
Author_Institution :
Dept. of Electr. Eng. & Comput. Eng., Univ. of California-Irvine, Irvine, CA, USA
fYear :
2012
fDate :
Aug. 30 2012-Sept. 2 2012
Firstpage :
1
Lastpage :
6
Abstract :
A novel fault-tolerant adaptive wormhole routing function for Networks-on-Chips (NoCs) is presented. The routing function guarantees absence of deadlocks and livelocks up to two faulty channels. The routing logic does not require reconfiguration when a fault occurs. The routes themselves are dynamic. Based on the faults in the network, alternative routes are used to reroute packets. Routing decisions are based only on local knowledge, which allows for fast switching. Our approach does not use any costly virtual channels. As we do not prohibit cyclic dependencies, the routing function provides minimal routing from source to destination even in the presence of faults. We have implemented the architecture design using synthesizable HDL. To ensure deadlock freedom, we have extended a formally verified deadlock detection algorithm to deal with fault tolerant designs. For a 20×20 mesh, we have formally proven deadlock freedom of our design in all of the 2,878,800 configurations in which two channels are faulty. We supply experimental results showing the performance of our architecture.
Keywords :
fault tolerance; integrated circuit design; integrated circuit reliability; network routing; network-on-chip; fault-tolerant NoC architecture design; fault-tolerant adaptive wormhole routing function; formally verified deadlock detection algorithm; formally verified deadlock-free routing function; network-on-chips; routing decisions; routing logic; virtual channels; Circuit faults; Fault tolerance; Fault tolerant systems; Routing; Switches; System recovery;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Integrated Circuits and Systems Design (SBCCI), 2012 25th Symposium on
Conference_Location :
Brasilia
Print_ISBN :
978-1-4673-2606-3
Type :
conf
DOI :
10.1109/SBCCI.2012.6344433
Filename :
6344433
Link To Document :
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