• DocumentCode
    2035934
  • Title

    Interleaved sepic converter with low switching loss

  • Author

    Lin, Bor-Ren ; Chen, Po-Li ; Chen, Jyun-Ji

  • Author_Institution
    Dept. of Electr. Eng., Nat. Yunlin Univ. of Sci. & Technol., Yunlin, Taiwan
  • fYear
    2010
  • fDate
    21-24 Nov. 2010
  • Firstpage
    1817
  • Lastpage
    1822
  • Abstract
    An interleaved sepic converter with low turn-on switching loss is presented in this paper. Power switches can be turned on with zero-voltage-switching (ZVS) feature when it is operated at duty cycle greater than 0.5. Although, the proposed converter is operated at hard switching when the duty cycle is less than 0.5, the smooth current by the resonant inductance can reduce the turn-on switching loss. Thus the total switching losses can be reduced compared to the hard switching converter. The interleaved PWM scheme can also reduce the current ripple at the input and output capacitors. Thus the size of inductor and capacitor can be reduced. The circuit configuration, operational principles and design considerations of the proposed converter are discussed in detail. Finally, simulations and experiments from a 120W laboratory prototype are provided to confirm the theoretical analysis and the advantages of the proposed converter.
  • Keywords
    PWM power convertors; zero voltage switching; ZVS; hard switching converter; interleaved PWM scheme; interleaved sepic converter; low switching loss; power 120 W; power switches; resonant inductance; turn-on switching loss; zero-voltage-switching; Zero voltage switching (ZVS); converters; interleaved PWM;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    TENCON 2010 - 2010 IEEE Region 10 Conference
  • Conference_Location
    Fukuoka
  • ISSN
    pending
  • Print_ISBN
    978-1-4244-6889-8
  • Type

    conf

  • DOI
    10.1109/TENCON.2010.5685946
  • Filename
    5685946