A PLL for clock generation with automatic frequency control under TID effects

Author

Dallasen, Ricardo Vanni ; Wirth, Gilson Inácio ; Both, Thiago Hanna

Author_Institution

Dept. of Electr. Eng., Fed. Univ. of Rio Grande do Sul, Porto Alegre, Brazil

fYear

2012

fDate

Aug. 30 2012-Sept. 2 2012

Firstpage

1

Lastpage

5

Abstract

This paper presents a PLL scheme for clock generation with a Total Ionizing Dose (TID) degradation detector. Externally to the PLL circuitry, when the degradation due to TID effects reaches a certain predefined threshold, the circuit reduces the clock frequency output. To compensate for the increased delay caused by the total dose effect (TID), the system increases the clock period in order to avoid timing violations, increasing the chip lifespan. The circuit was designed in a 0.35μm CMOS process and simulated with HSPICE tool.

Keywords

CMOS integrated circuits; frequency control; phase locked loops; radiation effects; CMOS process; HSPICE tool; PLL circuitry; PLL scheme; TID degradation detector; TID effects; automatic frequency control; chip lifespan; clock frequency output; clock generation; timing violations; total dose effect; total ionizing dose; Charge pumps; Clocks; Degradation; Phase frequency detector; Phase locked loops; Voltage control; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits and Systems Design (SBCCI), 2012 25th Symposium on

Conference_Location

Brasilia

Print_ISBN

978-1-4673-2606-3

Type

conf

DOI

10.1109/SBCCI.2012.6344441

Filename

6344441