Design of ADPLL for good phase and frequency tracking performance

This paper describe a new all-digital phase-locked loop (ADPLL). We reconfigure the commercially available ADPLL 74HC297 with a newly developed digitally controlled oscillator (DCO) to obtain digitally a phase-frequency detector (PFD) which achieves good phase and frequency error detection performance not implemented in 74HC297. A complete VHDL RTL level design is developed and fully synthesized for both 74HC297 and the proposed ADPLL. The VHDL code is targeted to FPGA technology (Altera, Xilinx) and standard cell ASIC (Alcatel 0.5 micron technology). Simulation of the proposed ADPLL and 74HC297 shows good tracking and homogeneous output of the proposed ADPLL.