Top-down design for Low power Multi-bit Sigma-Delta Modulator

The present paper reports a top-down design for the design of a Low Power Sigma-Delta Modulator, going from determining the architecture and specifications to the transistor-level design. A Multi-bit CIFF (Chain of Integrators with Feed Forward) implementation was chosen for low power consumption. The Sigma-Delta Modulator is designed in the 0.18 μm IBM CMOS technology and has a 98dB Dynamic Range, 2 V_pp Full Scale, and 20-20 kHz input bandwidth (Audio Bandwidth). The final circuit reached a simulated power consumption of 2.77 mW (Cadence), for 1.8 V power supply.