Kernel analysis for architecture design trade off in convolution-based image filtering

Intending to improve design trade offs in image processing architectures this work presents some kernel analysis for convolution-based image filtering. Some well-known filter kernels have been analyzed in order to identify symmetries and to allow the development of alternative architectures that can contribute to reduce power consumption and/or FPGA resources, maintaining or improving the overall system throughput. The separable kernel technique is also analyzed, and two architectures were developed and tested. Additionally, a technique based on overlapping kernels have been developed, analyzed and tested. All architectures were implemented and synthesized using Altera Quartus II EDA software and prototyped in four real-time image processing platforms. These platforms are composed by a CMOS camera, four Terasic FPGA development kits (with Altera devices) and an LCD. Synthesis, simulations and real-time results show the suitability of such architectures for this kind of design trade off.