Reconfigurable architecture of cube-connected cycle multiprocessor system

Recent advances in VLSI technology has stimulated research in massively parallel computers to satisfy the continuous increasing demand for computer power in advanced science and technology. The cube-connected cycle (CCC) is one of the most attractive interconnections and architectures for massively parallel computers. This paper addresses a new reconfigurable architecture to implement the cube-connected cycle on a silicon wafer by wafer scale integration (WSI), which is expected as a promising technology to construct massively parallel computers on silicon wafers. The performance of the proposed architecture is discussed with respect to yields of system. It is confirmed by comparing with previous work that the reconfigurable architecture based on the row-column redundant scheme achieves the better yield enhancement than earlier designs.<>