DocumentCode :
2036322
Title :
Sixth IEEE International High-Level Design Validation and Test Workshop
fYear :
2001
fDate :
9-9 Nov. 2001
Abstract :
The following topics were discussed: Design validation of microprocessors; techniques for high level design validation and test; state-of-the-art formal verification techniques; high level verification and analysis; high level timing verification and testing; verification of real life designs; high-level specification and verification; high-level test generation and coverage and analysis improved techniques for Boolean reasoning
Keywords :
formal specification; formal verification; hardware description languages; hardware-software codesign; high level synthesis; microprocessor chips; Boolean reasoning; coverage analysis; high level timing verification; high-level design test; high-level design validation; high-level specification; microprocessors; state-of-the-art formal verification techniques;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High-Level Design Validation and Test Workshop, 2001. Proceedings. Sixth IEEE International
Conference_Location :
Monterey, CA, USA
Print_ISBN :
0-7695-1411-1
Type :
conf
DOI :
10.1109/HLDVT.2001.972798
Filename :
972798
Link To Document :
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