Design and analysis of low power 1-bit full adder cell

In this paper low power full adder using 11 transistors has been proposed. The main idea of design is based on improving the performance of 10 transistor full adder design mentioned in literature by sacrificing a transistor count. While the proposed circuit has negligible area overhead, it has remarkably improved power consumption and temperature sustainability when compared with existing design. BSIM3v3 90 nm standard models are used for simulations on Tanner EDA tool.