Title :
Design and analysis of low power 1-bit full adder cell
Author :
Sinha, Deepa ; Sharma, Tripti ; Sharma, K.G. ; Singh, B.P.
Author_Institution :
Dept. of Electron. & Commun. Eng., FET-MTS, Lakshmangarh, India
Abstract :
In this paper low power full adder using 11 transistors has been proposed. The main idea of design is based on improving the performance of 10 transistor full adder design mentioned in literature by sacrificing a transistor count. While the proposed circuit has negligible area overhead, it has remarkably improved power consumption and temperature sustainability when compared with existing design. BSIM3v3 90 nm standard models are used for simulations on Tanner EDA tool.
Keywords :
adders; logic design; low-power electronics; BSIM3v3 standard models; Tanner EDA tool; low power full adder cell; power consumption; size 90 nm; transistor full adder design; word length 1 bit; Adders; Logic gates; MOSFETs; Power demand; Very large scale integration; GDI; XOR gate; nMOS; pMOS;
Conference_Titel :
Electronics Computer Technology (ICECT), 2011 3rd International Conference on
Conference_Location :
Kanyakumari
Print_ISBN :
978-1-4244-8678-6
Electronic_ISBN :
978-1-4244-8679-3
DOI :
10.1109/ICECTECH.2011.5941706
