Title :
Estimating the relative single stuck-at fault coverage of test sets for a combinational logic block from its functional description
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
When the gate-level description of a logic block is unknown, it may become necessary to estimate the gate-level stuck-at fault coverage of a test set for the block by using a fault coverage metric that does not require simulation of gate-level faults. We propose such a metric based on stuck-at faults on primary inputs of the block We show that the proposed metric is accurate in predicting the relative gate-level stuck-at fault coverage of different test sets
Keywords :
combinational circuits; high level synthesis; logic testing; combinational logic block; fault coverage metric; gate-level faults; primary inputs; relative single stuck-at fault coverage; Circuit faults; Circuit simulation; Circuit synthesis; Circuit testing; Cities and towns; Delay; Logic gates; Logic testing; Predictive models;
Conference_Titel :
High-Level Design Validation and Test Workshop, 2001. Proceedings. Sixth IEEE International
Conference_Location :
Monterey, CA
Print_ISBN :
0-7695-1411-1
DOI :
10.1109/HLDVT.2001.972804
