• DocumentCode
    2036502
  • Title

    Practical use of sequential ATPG for model checking: going the extra mile does pay off

  • Author

    Hsiao, Michael ; Jain, Jawahar

  • Author_Institution
    Bradley Dept. of Electr. & Comput. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    39
  • Lastpage
    44
  • Abstract
    We present a study of the practical use of a simulation-based automatic test pattern generation (ATPG) for model checking in large sequential circuits. Preliminary findings show that ATPGs which gradually build and learn from the state-space has the potential to achieve the verification objective without needing the complete state-space information. The success of verifying a useful set of properties relies on the performance and capacity of ATPG. We compared an excitation-only ATPG with one that performs both excitation and propagation. Even though the excitation-only strategy suffices to justify the objective, the excitation-and-propagation ATPG achieved higher signal-justification coverages than the excitation-only counterpart. This is because excitation-only ATPG falls short in obtaining pertinent state information helpful for traversing the state space, resulting in ATPG aborting the objective. Our experiments demonstrated that incomplete but useful information learned via propagation can have significant impact on the performance of ATPG for model-checking
  • Keywords
    automatic test pattern generation; binary decision diagrams; formal verification; high level synthesis; sequential circuits; excitation-only strategy; large sequential circuits; model checking; simulation-based automatic test pattern generation; state information; state-space; verification objective; Automatic test pattern generation; Binary decision diagrams; Boolean functions; Circuit simulation; Computational modeling; Computer simulation; Data structures; Explosions; Sequential circuits; State-space methods;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High-Level Design Validation and Test Workshop, 2001. Proceedings. Sixth IEEE International
  • Conference_Location
    Monterey, CA
  • Print_ISBN
    0-7695-1411-1
  • Type

    conf

  • DOI
    10.1109/HLDVT.2001.972805
  • Filename
    972805