Title :
Specification of interface behavior for the automatic generation of bus-interface models
Author :
Birmingham, William P. ; Daga, Ajay J. ; DeKock, Jonathan L.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Abstract :
This paper describes SpecIT, a tool that captures a high-level specification of bus-interface behavior and automatically generates VHDL and Verilog models. SpecIT users need not be familiar with either VHDL or Verilog, instead interface behavior is specified graphically using familiar hardware constructs such as state diagrams, timing diagrams, and truth tables. SpecIT substantially reduces the time required to create bus-interface models
Keywords :
formal specification; hardware description languages; logic CAD; logic design; system buses; SpecIT; VHDL models; Verilog models; bus-interface behavior; bus-interface models; high-level specification; interface behavior specification; state diagrams; timing diagrams; truth tables; Circuit simulation; Computational modeling; Computer aided engineering; Computer interfaces; Design engineering; Digital systems; Hardware design languages; Microprocessors; Signal generators; Timing;
Conference_Titel :
Electro/94 International. Conference Proceedings. Combined Volumes.
Conference_Location :
Boston, MA
Print_ISBN :
0-7803-2630-X
DOI :
10.1109/ELECTR.1994.472681
