DocumentCode :
2036537
Title :
Symbolic simulation techniques-state-of-the-art and applications
Author :
Blank, Claudia ; Eveking, Hans ; Levihn, Jens ; Ritter, Gerd
Author_Institution :
Dept. of Electr. Eng. & Inf. Technol., Darmstadt Univ. of Technol., Germany
fYear :
2001
fDate :
2001
Firstpage :
45
Lastpage :
50
Abstract :
A number of different techniques of symbolic simulation in particular at the behavioral and structural rt-level are classified. The principles of the TUD Symbolic Simulator used for equivalence checking are briefly outlined. The application of the tool to property checking is demonstrated. Experimental results with input languages Esterel and C are given
Keywords :
C language; circuit CAD; formal verification; high level synthesis; C; Esterel; TUD Symbolic Simulator; behavioral rt-level; input languages; property checking; structural rt-level; symbolic simulation; Context modeling; Electronic mail; Engines; Equations; Humans; Inference algorithms; Information technology; Inspection; Logic;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High-Level Design Validation and Test Workshop, 2001. Proceedings. Sixth IEEE International
Conference_Location :
Monterey, CA
Print_ISBN :
0-7695-1411-1
Type :
conf
DOI :
10.1109/HLDVT.2001.972806
Filename :
972806
Link To Document :
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