A 4-Bits CSA Adder Using the Arithmetic A2 Redundant Binary Representation for Mixed Neural Networks with On-Chip Learning

Author

Boukadida, Hatem ; Gafsi, Zied ; Hassen, Nejib ; Besbes, Kamel

Author_Institution

Micro-Electron. & Instrum. Lab., Fac. of Sci. of Monastir, Monastir

fYear

2008

fDate

26-28 June 2008

Firstpage

97

Lastpage

98

Abstract

This paper presents a time-efficient 4-bits carry select adder (CSA) using the arithmetic A2 redundant binary representation. This structure is very suitable for implementation in VLSI of simple mixed-signal neural networks with on-chip learning. This adder is based on a classical weighted binary carry-select adder with two input/output trans-coders. Comparisons with another FPGA-based A2 adder show that the proposed CMOS structure offers a significant increase in speed, while consuming a little more area.

Keywords

adders; neural chips; redundant number systems; 4-bits CSA; CMOS structure; FPGA; VLSI; arithmetic A2 redundant binary representation; carry select adder; mixed neural networks; on-chip learning; Adders; Artificial neural networks; Circuits; Computer networks; Digital arithmetic; Digital-analog conversion; Network-on-a-chip; Neural networks; Neurons; Very large scale integration; arithmetic circuits; neural networks; redundant binary representations;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Information Systems and Industrial Management Applications, 2008. CISIM '08. 7th

Conference_Location

Ostrava

Print_ISBN

978-0-7695-3184-7

Type

conf

DOI

10.1109/CISIM.2008.18

Filename

4557841