DocumentCode
2036646
Title
Test pattern generation for timing-induced functional errors in hardware-software systems
Author
Arekapudi, Srikanth ; Xin, Fei ; Peng, Jinzheng ; Harris, Ian G.
Author_Institution
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
fYear
2001
fDate
2001
Firstpage
83
Lastpage
88
Abstract
We present an ATPG algorithm for the covalidation of hardware-software systems. Specifically, we target the detection of timing-induced functional errors in the design by using a design fault model which we propose. The computational time required by the test generation process is sufficiently low that the ATPG tool can be used by a designer to achieve a significant reduction in validation cost
Keywords
automatic test pattern generation; computational complexity; hardware-software codesign; logic testing; timing; ATPG algorithm; computational time; covalidation; design fault model; hardware-software systems; test pattern generation; timing-induced functional errors; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
High-Level Design Validation and Test Workshop, 2001. Proceedings. Sixth IEEE International
Conference_Location
Monterey, CA
Print_ISBN
0-7695-1411-1
Type
conf
DOI
10.1109/HLDVT.2001.972812
Filename
972812
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