Using live sequence charts for hardware protocol specification and compliance verification

Interface standard specification documents are notoriously difficult to read and interpret consistently. The advent of the system-on-chip design paradigm compounds the problem as multiple vendors attempt to interpret the standard consistently. Monitors, while popular for formal and semiformal verification, do not offer a readable, high-level description. We propose using Live Sequence Charts to specify hardware standards using a recent Virtual Sockets Interface Alliance standard as a running example