DocumentCode
2036737
Title
Proving sequential consistency by model checking
Author
Braun, Tim ; Condon, Anne ; Hu, Alan J. ; Juse, Kai S. ; Laza, Marius ; Leslie, Michael ; Sharma, Rita
Author_Institution
Dept. of Comput. Sci., Tech. Univ. of Darmstadt, Germany
fYear
2001
fDate
2001
Firstpage
103
Lastpage
108
Abstract
Sequential consistency is a multiprocessor memory model of both practical and theoretical importance. Unfortunately, the general problem of verifying that a finite-state protocol implements sequential consistency is undecidable, and in practice, validating that a real-world, finite-state protocol implements sequential consistency is very time-consuming and costly. In this work, we show that for memory protocols that occur in practice, a small amount of manual effort can reduce the problem of verifying sequential consistency into a verification task that can be discharged automatically via model checking. Furthermore, we present experimental results on a substantial, directory-based cache coherence protocol, which demonstrate the practicality of our approach
Keywords
cache storage; finite state machines; memory protocols; cache coherence protocol; finite state protocol; memory protocols; model checking; multiprocessor memory model; sequential consistency; Access protocols; Application software; Coherence; Computer science; Councils; Error correction; Hardware; Interleaved codes; US Department of Transportation;
fLanguage
English
Publisher
ieee
Conference_Titel
High-Level Design Validation and Test Workshop, 2001. Proceedings. Sixth IEEE International
Conference_Location
Monterey, CA
Print_ISBN
0-7695-1411-1
Type
conf
DOI
10.1109/HLDVT.2001.972815
Filename
972815
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