Title :
Hardware-software covalidation: fault models and test generation
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Abstract :
The increasing use of hardware-software systems in cost-critical and life-critical applications has led to heightened significance of design correctness of these systems. This paper presents a summary of research in hardware-software covalidation winch involves the verification of design correctness using simulation-based techniques. This paper focuses on the test generation process for hardware-software systems as well as the fault models and fault coverage analysis techniques which support test generation
Keywords :
automatic test pattern generation; formal verification; hardware-software codesign; design correctness; fault coverage analysis; fault models; hardware-software covalidation; hardware-software systems; simulation-based techniques; test generation process; verification; Application software; Automatic testing; Costs; Design methodology; Formal verification; Hardware; Life testing; Signal processing; Software testing; System testing;
Conference_Titel :
High-Level Design Validation and Test Workshop, 2001. Proceedings. Sixth IEEE International
Conference_Location :
Monterey, CA
Print_ISBN :
0-7695-1411-1
DOI :
10.1109/HLDVT.2001.972822
