DocumentCode :
2037546
Title :
Optimizations in max-log-MAP LLRe VLSI architecture
Author :
Perez, Jesus M. ; Fernandez, Victor
Author_Institution :
Microelectron. Eng. Group, Cantabria Univ., Santander, Spain
Volume :
1
fYear :
2005
fDate :
14-15 July 2005
Firstpage :
359
Abstract :
One of the most popular channel iterative decoding systems is the BCJR (MAP) decoding algorithm. It is used in turbo code schemes, and has enabled them to reach 1dB from Shannon´s theoretical limit. This kind of algorithm requires a large area and, therefore, any area saving, without penalty in critical path or BER performance, would be worthwhile. A new scheme is presented for the computation of LLRe values in MAP-based systems. Based on exploiting the convolutional code Trellis properties, this scheme saves from 27 to 52% of the required area in LLRe calculations, with a small penalty in critical path and without any change in BER performance.
Keywords :
VLSI; convolutional codes; iterative decoding; maximum likelihood decoding; optimisation; trellis codes; turbo codes; BCJR decoding algorithm; BER performance; MAP-based system; Shannon theoretical limit; Trellis property; VLSI architecture; channel iterative decoding system; convolutional code; critical path; max-log-MAP LLRe; turbo code scheme; Bit error rate; Code standards; Convolutional codes; Digital video broadcasting; Iterative algorithms; Iterative decoding; Microelectronics; Turbo codes; Very large scale integration; Viterbi algorithm;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signals, Circuits and Systems, 2005. ISSCS 2005. International Symposium on
Print_ISBN :
0-7803-9029-6
Type :
conf
DOI :
10.1109/ISSCS.2005.1509928
Filename :
1509928
Link To Document :
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