A prototype chip of reconfigurable logic device using variable grain logic cell architecture

We propose a variable grain logic cell (VGLC) architecture. Its key feature is variable granularity which helps to create a balance between two types of devices: coarse-grain type and fine-grain type. Because of this, the VGLC can achieved high-performance on any applications. In this paper, we describe the VGLC prototype chip designed in e-Shuttle 65nm library. In addition, in order to implement circuits, we newly developed the configuration bit stream generator. In the evaluation with benchmarks, the VGLC with only logic function uses 36%-97% of logic blocks more than LUT-based FPGA. However, the arithmetic functions of VGLC greatly contributed to the device performance, VGLC achieved a half of device area compared to FPGA.