High-level implementation of the 5-stage pipelined ARM9TDM core

This paper summarizes a project on the implementation of the ARM9TDM, a 32-bit RISC processor based on the ARM9TDMI. This core is the successor to the ARM7TDMI-S which is used for embedded applications requiring low power, small chip area, and high processing speed. The main features of the ARM9TDM are its use of a 5-stage pipelined datapath and a Harvard architecture that has separate data and instruction interfaces. It supports the ARMv4T instruction set architecture (ISA) that uses both the 32-bit ARM instructions and 16-bit Thumb instructions. It includes a high-speed multiplier and debug capabilities using JTAG boundary scan test interface. It does not include an EmbeddedICE-RT module. The project was coded using the Verilog Hardware Description Language and was simulated using Synopsys VCS. The verified code was synthesized in 0.25-micrometer standard cells using Synopsys Design Vision. The layout generated by Synopsys Astro was characterized as having a maximum operating frequency of 34.13 MHz, an average power consumption of 16 mW and a chip size of 1.5335 sq. mm.