Title :
Design of a gate array matrix processor
Author_Institution :
Nanyang Technol. Univ., Singapore
Abstract :
The design of a matrix arithmetic processor using the Gould CMOS 2-μm gate array design kit is described. The background leading to the formulation of the matrix arithmetic processor is presented, along with its design, implementation, simulation and analysis. A 16-bit floating-point format is proposed.
Keywords :
CMOS integrated circuits; digital arithmetic; logic arrays; matrix algebra; network analysis; network synthesis; 16 bit; 16-bit floating-point format; 2 micron; Gould CMOS 2-micron gate array design kit; analysis; design; gate array matrix processor; implementation; matrix arithmetic processor; simulation; Adders; Analytical models; Arithmetic; CMOS process; CMOS technology; Computational modeling; Equations; Process design;
Conference_Titel :
TENCON '93. Proceedings. Computer, Communication, Control and Power Engineering.1993 IEEE Region 10 Conference on
Conference_Location :
Beijing, China
Print_ISBN :
0-7803-1233-3
DOI :
10.1109/TENCON.1993.320052
