On placement of logic schematics

We consider the problem of determination of the sequence of n modules of a logic schematic, that results in a minimum number of line intersections. We consider the case when the logic schematic consists of a union of zero or more P/sub r/,K/sub p,q/ and C/sub 2m/. We use a graph theoretic approach and present an algorithm of time complexity O(n) for sparse schematics and O(n/sup 3/) for dense schematic.<>