PLL Jitter Analysis with Various Power Delivery Networks on a Board

Increasing frequency and reducing time margin have made desigen of power delivery neworks (PDNs) on board to be an integral part of chip designs. Power delivery network designs are usually achieved by mounting the decoupling capacitors on power plates so that the designed power impedance is relatively lower on the interested frequency ranges. But, some parts out of frequency-dependant impedance profile of power delivery networks that make the major effect on noise performances of digital, RF, and analog chips does not be very clear according to chip´s family. In this paper, we demonstrate the analysis of power delivery networks for the multiple voltage domains on an analog PLL jitter performance. We look for self impedances of chip mounted on board according to decoupling capacitor´s size, their positions, and DC-DC chip. We analyze the PLL´s jitter characteristics depending on self-impedance profiles for core and IO circuit. Through this work, it is clear that the PDNs design concept which is considering inherent operation characteristics should be adapted for the efficient and costive system.